Device Family: Arria® II GZ, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why are the DDR3 controller write-to-read and read-write turnaround times longer than expected?

Description

For UniPHY-based DDR3 memory controllers, the turnaround times are calculated using the following equations:


Read-to-write turnaround = ‘CAS latency’ – ‘CAS write latency’ + (‘Burst length’ / 2) + 2 + ‘Read-to-write OCT turnaround’

 

Write-to-read turnaround = ‘CAS write latency’ + (‘Burst length’ / 2) + tWTR + ‘Write-to-read OCT turnaround’

 

The read-to-write and write-to-read OCT turnaround times refer to the number of additional clock cycles needed to change the OCT termination from input to output termination and vice versa. The value of each turnaround time in memory clock cycles can be found in the <variation_name>_c0.v file.

 

The burst length is always 8 (BL8) for DDR3.