Device Family: Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers, Errata

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface?

Description

When comparing the DQ waveforms, you may notice that the measured steady-state read waveform amplitude exceeds the expected value simulated by the IBIS model. This is due to an adjustment of the Rt termination value by the Quartus® II software where the equivalent resistance is higher than expected.

Workaround/Fix