Device Family: Stratix® III

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR2 SDRAM Controller supporting ALTMEMPHY

Why do the DQS and DQSn signals generated by the DDR SDRAM and DDR2 SDRAM High-Performance Controllers I for write operations have an additional pulse at the end of a write burst?

Description

There is an issue with the AFI-based DDR and DDR2 SDRAM High-Performance Controllers I (HPC I) which causes the DQS and DQSn signals to generate an extra pulse after a write burst as shown in Figure 1 below.

Figure 1

This issue affects designs that use the half-rate DDR and DDR2 SDRAM HPC I targeting Stratix® IV, Stratix III and Arria® II GX devices. AFI-based DDR and DDR2 SDRAM HPC in full-rate mode are not affected.

This issue will not cause any functional problem to your system if you are using the DM pin. As the extra pulse is generated after a write burst, the extra pulse will not cause incorrect data to be written into the SDRAM because the controller asserts the DM pin high after the write burst.

The DDR and DDR2 SDRAM HPC II are not affected by this issue.