Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property

IP Product: Triple Speed Ethernet with 1588 MegaCore

Why do I see hold time violations in Triple Speed Ethernet IP Core with Quartus II v15.0?


Due to a problem in Quartus® II software version 15.0, you may see marginal hold time violation especially in multi-channel Triple Speed Ethernet IP Core designs that target Arria® V, Arria® 10 , Cyclone® V and Stratix® V device families.


 To work around this issue, add the following Synopsys Design Constraint file (.sdc) constraints for Fitter into your project SDC file.
if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {

      set_min_delay -from  [get_keepers {*<tse_entity_name>*}]  -to  [get_keepers {*<tse_entity_name>*}] 0.0ns

   } else {

      set_min_delay -from  [get_keepers {*<tse_entity_name>*}]  -to  [get_keepers {*<tse_entity_name>*}] <value>



*Note: Increase the “<value>” from “0.1ns” to “0.2ns” if the hold time violation persisted.


Refer to “Table 2-2: Recommended Quartus II Pin Assignments” in Triple-Speed Ethernet MegaCore Function User Guide for other related recommendations.

For TSE IP with IEEE 1588v2 feature enabled and target Arria V device family, apply the following patch in addition to the workaround above:
Please download the appropriate Quartus® II software version 15.0 patch 0.14 from the following links:



This is scheduled to be fixed in a future release of the Quartus II software.