Device Family: Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does my ALTDQ_DQS2 design have conflicting warning messages?

Description

When you design with the ALTDQ_DQS2 megafunction in Stratix® V in Quartus II software version 11.1SP2 and earlier, you may encounter the following conflicting warnings:

Warning (129000): Input port PHASECTRLIN on atom "<hierarchy>|vm_altdq_dqs2_stratixv:altdq_dqs2_inst|dqs_delay_chain", which is a stratixv_dqs_delay_chain primitive, is not legally connected and/or configured
    Info (129003): Input port PHASECTRLIN[0] is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
    Info (129003): Input port PHASECTRLIN[1] is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
    Info (129007): Compiler expects input port PHASECTRLIN to be disconnected because the stratixv_dqs_delay_chain atom "<hierarchy>|vm_altdq_dqs2_stratixv:altdq_dqs2_inst|dqs_delay_chain" has its use_phasectrlin parameter is set to "FALSE"

You may get similar warnings for ENAPHASETRANSFERREG, RST, and PHASEINVERTCTRL ports.

Workaround/Fix

The warnings are harmless. The workaround is to disconnect the ports that are specified in the warning. Once the ports are disconnected, the warnings should go away.

 

This issue will be fixed in a future release of the Quartus® II software.