The Design Assistant tool will generate R105 warnings if it detects a reset signal that is generated in one clock domain and used in another clock domain. This warns the user of a potential metastability issue if the signal is not properly synchronized.
All reset input signals to the UniPHY-based DDR3 controller are synchronized to the respective clock domains. You can safely ignore any reset warnings that apply to the logic within the DDR3 controller. The paths are either asynchronous reset signals going to a reset synchronizer, or asynchronous signals that are carefully timed to avoid metastability issues.