Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property

IP Product: PCI Express 1/2/4/8 Lanes (x8)

Why does my PCIe Development Kit not enumerate and/or show up on the link after loading an SOF programming file?


Due to an issue with some BIOS and some OS, notably CentOS 6, the link cannot automatically enumerate the Altera® Hard IP for PCI® Express if the FPGA is configured after the BIOS/OS discovery phase has completed.


Press the reset button on the motherboard so that a warm reset occurs (one in which the power is kept on so the FPGA image is retained). In most cases this should cause the BIOS/OS to re-discover connected devices and allow the FPGA to be seen on the PCIe link.

Alternatively, ensure that the dev kit is configured before the BIOS/OS discovery phase starts from cold reset (within 100ms). To do this either power the dev kit externally and only power on the motherboard once the FPGA is configured or ensure the FPGA is configured using FPP mode.