Device Family: Arria® V GT, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Stratix® IV GX, Stratix® V E

Type: Answers

Area: EMIF, Intellectual Property

IP Product: RLDRAM II Memory Controller

Why is the afi_half_clk signal not constrained in my UniPHY-based memory controller?


Due to a problem in the Quartus® II software version 12.1 and later, UniPHY-based memory controllers are missing SDC constraints to properly constrain the afi_half_clk clock leading to incorrect timing analysis for the afi_half_clk clock domain.


If the design is not using the afi_half_clk signal, no changes need to be made.

If the design is using the afi_half_clk signal, add a create_generated_clock assignment for afi_half_clock to the top-level SDC file. If there is no top-level SDC file, create one and add it to the project file list.

This issue will be fixed in a future version of the Quartus II software.