Device Family: Stratix® IV, Stratix® IV E, Stratix® IV GT, Stratix® IV GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Warning (15610): No output dependent on input pin "avl_burstbegin"

Description

The avl_burstbegin signal is part of our Avalon-MM specification; it is used to indicate a start of burst transaction.

Prior to Quartus
® II software version 11.0, the avl_burstbegin signal was used by DDR2 and DDR3 SDRAM controller to detect new Avalon burst commands.

But after Quartus
II software version 11.0, there were changes made in the architecture of the DDR2 and DDR3 SDRAM controller. In this new architecture, avl_burstbegin signal is not being used to detect incoming Avalon burst commands.

To support backward compatibility of Quartus II software version, Altera did not remove the avl_burstbegin signal although this signal is not required.

Workaround/Fix

Quartus® II software will optimize out the avl_burstbegin during synthesis operation since the signal has zero fan-out

You can ignore this warning message since avl_burstbegin signal is not required and hence is being optimize away.