Device Family: Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers, How-To

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is my UniPHY External Memory Interface Toolkit timing out?


DDR2 and DDR3 SDRAM designs will hang the External Memory Interfaces (EMIF) debug toolkit when the core fails the Read calibration VFIFO stage. This is a known issue in Quartus® II software version 11.1 through 11.1SP2. The debug toolkit eventually times out with the following error message:

Could not get response back from processor within allowed time!


The workaround is to increase the timeout count in the system console Tcl script. Here are the steps to implement the workaround:

1)  Open the nios_phy_111.tcl file in the following directory:


2) Search for the variable MAX_PROC_LOOP and change it to 4000 as shown below. This variable specifies the number of seconds the debug toolkit will wait to hear back from the Nios sequencer before timing out:

      # The maximum number of times we can go through the sleep loop waiting for the processor

      variable MAX_PROC_LOOP 4000

3) Reopen the debug toolkit and connect to the Stratix V device. It may take several minutes to connect but it should connect and tell you which stage of calibration failed.