Device Family: Stratix® IV, Stratix® IV E, Stratix® IV GT

Type: Answers

Area: EMIF, Intellectual Property

IP Product: QDRII SRAM Controller

Error (10231): Verilog HDL error at <variation_name>_memphy_top.v(305): value cannot be assigned to input "pll_mem_clk"


In Quartus® II software versions 9.1, 9.1 SP1 and SP2, there is an issue in the file <variation_name>_memphy_top.v  that occurs when generating a full rate UniPHY QDRII interface with the "Master for PLL/DLL sharing" option not selected.


The workaround is to make these changes.  and then recompile.


1. In the file <variation_name>_memphy_top.v  comment out this line.


            assign pll_mem_clk = pll_afi_clk;


2. In file <variation_name>_example_top.v where the instantiation is


<variation_name> mem_if (


.pll_mem_clk  (pll_mem_clk),




change this line to


.pll_mem_clk   (pll_afi_clk)


Recompile the project.


If you re-generate the IP, remember to repeat these changes. This issue is expected to be fixed in a later version of Quartus II software.