Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

Can the 128-bit Avalon-MM Txs slave interface of the Altera Hard IP for PCI Express handle read/write request with ByteEnable=0x01 ?

Description

Due to a problem in the Quartus® II software version 13.1 and earlier, the 128-bit Avalon-MM® Txs slave interface of the Hard IP for PCI Express® cannot generate a correct PCI Express TLP packet when the ByteEnable = 0x01, 0x03, or 0x7 at Avalon-MM interface.

Avalon-MM bridges operate correctly with a burst count = 1 and the following byte enables (DW Byte Enable)

16'hF000
16'h0F00
16'h00F0
16'h000F
16'hFF00
16'h0FF0
16'h00FF
16'hFFF0
16'h0FFF
16'hFFFF

Workaround/Fix

Use 64bit Avalon-MM Txs slave interface, or set ByteEnable to more than 0x07 (set 4 byte enable or more) with 128-bit Avalon-MM Txs slave interface within Quartus II software version 13.1 and earlier.

This problem is scheduled to be fixed in a future release of the Quartus II software.