During the FIRST time the Dynamic reconfiguration controller initiates a read /write, for example to change or read the PMA controls(VOD, preemphasis, equalization or dc gain), the transceiver channel switches permanently from the registers that contain static transceiver settings to registers that are written by the dynamic reconfiguration controller. Due to this asynchronous switching, there may a few bit errors and transitions in the transceiver status signals.
During our experiments, we have observed two to five parallel cycles of transmit data getting corrupted for the first time the dynamic reconfig controller performs a PMA control reconfiguration. This resulted in few bit errors in the transmitted serial data. You can also expect transitions on the receiver status signals such as rx_freqlocked for about five receive side parallel clock cycles.
To workaround this issue, perform a read or write operation from the dynamic reconfiguration controller during system bring up/initialization so that the above mentioned register switching is done before normal system operation.