The RapidIO core has its own reset control module which handles the reset sequence if the link goes down, as in the case of a cable pull. When the cable is pulled, the receiver will detect line errors and lose frequency lock. The reset controller will keep the RapidIO core in reset until the transceiver has been able to re-establish freqency lock. Once frequency lock has been achieved, the RapidIO core is released from reset and its Port Initialization process begins. The process includes lane synchronization and lane alignment as described in RapidIO 1.3 Specification. After exchanging the required Status Control Symbols, the link is up and ready to exchange Serial RapidIO packets.
You can monitor the status of the link by sampling the following error signals.
You can also monitored the Port 0 Error and Status CSR, Offset 0x158. Ths register keeps track of the input and output state machines and reports if the port is initialized or if there is a current error.
Please consult the RapidIO MegaCore Function User Guide (PDF) for more details on Error Detection and Recovery. A complete section is dedicated to this topic.