Device Family: Cyclone® V GX

Type: Answers

Area: Component

Area: EMIF

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does the avl_ready signal stay low when using the hard memory controller with multi-port front end port widths of 128 bits?


Due to an issue in the hard memory controller in the Quartus® II software version 12.1sp1, the avl_ready signal will stay low if using 128-bit width ports. Calibration may pass successfully, but the controller will not assert the avl_ready signal.


To work around this issue, it is recommended to use port widths of 64 or less.

This issue has been fixed in Quartus II software version 13.0sp1.