Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: Low Latency 100Gbps Ethernet MAC and PHY MegaCore

How can I find an explanation for the SYNOPT_FULL_SKEW, RST_CNTR, and CREATE_TX_SKEW parameters in the Low Latency 40- and 100-Gbps Ethernet IP core simulation test bench?

Description

The following simulation parameters in the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore® function test bench file are not explained in the user guide.  Please refer to the following definitions:

SYNOPT_FULL_SKEW - Support full skew tolerance according to IEEE spec. In the example testbench this is turned off to speed up the initialization time

RST_CNTR - controls the reset delays for the PMA reset process. It's set to 6 in simulation to speed up initialization. Ignore this parameter for synthesis and leave at the default value.

CREATE_TX_SKEW - Lane to lane skew in simulation.

It’s important that user should not modify these parameters, otherwise simulation could fail. These parameters are subject to removal in future Quartus® II releases.

Workaround/Fix

These definitions are not scheduled to be added to the documentation.
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