Device Family: Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I view the external memory signals in my HPS SDRAM simulation?

Description

The HPS simulation model does not use external memory pins to connect to the DDR2, DDR3 or LPDDR2  memory model. The actual memory model is created internally in the following hierarchy:

hps_0/fpga_interfaces/f2sdram/hps_sdram_inst/mem/

You will need to view the external signals at this level.