Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V ST

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

How do I calculate the ECC for DDR3 UniPHY based controller?

Description

The error correction code (ECC) calculation for UniPHY-based memory contollers is based on the Hamming Coding scheme. The Hamming Coding scheme derives the parity bits and appends them to the original data to produce the output code word. The number of parity bits appended depends on the width of the data.

For more information, refer to the ALTECC_ENCODER and ALTECC_DECODER megafunctions in the Integer Arithmetic Megafunctions User Guide.