Due to a limitation of the Quartus® II software version 13.1, It is not possible to alter the HPS-to-FPGA user clocks or other HPS clocks in Qsys.
When you enable HPS-to-FPGA user 0/ user 1 / user 2 clock in Qsys and set its clock frequency to a custom value, the preloader will have a different clock value in the pll_config.h file.
To workaround this limitation in the Quartus II software version 13.1 and earlier follow the steps below:
If you need to change any clocking parameters other than SDRAM clocking parameters, the pll_config,h file generated by the Pre-loader generator (bsp-editor) must be manually edited.
pll_config.h file is available in the BSP target directory: software\spl_<bsp name>\generated\ pll_config.h
Example configuration: HPS-to-FPGA user clock 0 (h2f_user0_clock) = 40 MHz with EOSC1 = 25 MHz
The C5 divider parameter would need to be changed as follows in the pll_config.h
- CONFIG_HPS_CLK_OSC1_Hz = 250000000 (for EOSC1 = 25 MHz)
- CONFIG_HPS_MAINPLLGRP_VCO_DENOM = 0 (for PLL denominator = 1)
- CONFIG_HPS_MAINPLLGRP_VCO_NUMER = 63 (for PLL numerator = 64)
- CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT = 39 (for C5 divider = 40)
Re-calculate the HPS-to-FPGA user 0 clock value setting for the above:
h2f_user0_clock = ESOC1 clock x ( PLL Numerator/PLL Denominator) / C5 divider = 25MHz x (64/1) / 40 = 40MHz
For further information see Preloader Clocking Customization - v13.1 on www.Rocketboards.org which contains a clocking calculator
http://www.rocketboards.org/foswiki/Documentation/PreloaderClockingCustomization131
The HPS Megawizard has been enhanced for the Quartus II software version 14.0 and later, and allows clocks to be set in Qsys.