Description
The TSE megafunction does not support multi port for 1000BASE-X/SGMII PCS only option with LVDS I/O.
You need to ensure that all the LVDS reference clocks are sharing the same clock and all LVDS I/O are located on the same side of the FPGA (left or right).
You don't need to merge the PLL manually. Quartus® II software will automatically merge all the PLL after the Fitter stage.