Device Family: Arria® V ST, Arria® V SX, Cyclone® V, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: UniPHY Controller

Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region

Description

You may experience the above fitter error when compiling a UniPHY-based memory controller in Cyclone® V SoC and Arria® V SoC device. The error occurs because the FPGA device does not have dual-regional clocks in certain portions of the chips.

Workaround/Fix

The workaround is to change pll_avl_clk, pll_config_clk, and pll_addr_cmd_clk from dual-regional clock to regional clock in the .QSF file as follows:

From:
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_addr_cmd_clk
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_avl_clk
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_config_clk

To:
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_addr_cmd_clk
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_avl_clk
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_config_clk