Article ID: 000075124 Content Type: Error Messages Last Reviewed: 04/11/2023

Error (175001): Could not place fractional PLL <PLL name>

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When expanding the above error message in the Quartus® II software, you might get the following error message when targeting a Stratix® V, Arria® V, and Cyclone® V device:

    Error (177020): The PLL reference clock input pin <pin name> was not placed in a dedicated input pin that can reach fractional PLL <PLL name>

    This error message pair is generated when trying to directly feed a fractional PLL with a CLKn pin.

    Resolution

    Place a clock contol block (ALTCLKCTRL megafunction) between the CLKn pin and the input port of the PLL as shown in the example below:

    Example:

    Figure 1

    Related Products

    This article applies to 14 products

    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Arria® V GT FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V SX SoC FPGA