Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I resolve timing violations on the quarter rate to half rate clock transfer in my UniPHY-based DDR3 controller design?

Description

When the UniPHY DDR3 controller in quarter rate mode is operated at or near the maximum frequencies specified in the External Memory Interface Spec Estimator Tool (HTML), you may see timing violations on the core timing paths from the quarter rate clock domain to the half rate clock domain.  These paths are of the form: *qr_to_hr|dataout_r* to *hr_to_fr*

Workaround/Fix

Over-constraining these paths can aid timing closure.  To over-constrain these paths for the fitter but not for Static Timing Analysis, include this constraint in your Synopsys Design Constrains (.sdc) file.

#Overconstraining QR to HR clock domain
set ver_info $::TimeQuestInfo(nameofexecutable)
if { != "quartus_sta"} {
set_max_delay -from [get_keepers *qr_to_hr\|dataout*] -to [get_keepers *hr_to_fr*] 1}

This constraint sets the maximum delay between these two nodes to a very short delay which causes the Quartus II fitter to prioritise these paths.