Device Family: Arria® II GZ, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Warning (10230): Verilog HDL assignment warning at *instance_name*_write_datapath.v(118): truncated value with size to match size of target (1)

Description

You may experience the above warning when compiling the DDR2 or DDR3 SDRAM Controller with UniPHY IP in Quartus II. 

This warning occurs as Quartus II synthesized away some of registers and logics that connected to the 'phy_ddio_oct_ena_pre_shift' signal due to undeclared bus for this signal in <instance name and hierarchy>_write_datapath.v file.  This lead to incorrect OCT switching behavior.

 

Workaround/Fix

Declare the \'phy_ddio_oct_ena_pre_shift\' signal as below in the generated <instance name>_write_datapath.v file before their assignment.

wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_pre_shift;