It is due to the reason that each LVDSs PLL reset input is driven by separate Triple Speed Ethernet s LVDS reset sequence logic and causes the reset input for each LVDSs PLL undriven by the same reset input source.
The following patch provides a solution to ensure different LVDS channels from different Triple Speed Ethernet IP MegaCore functions able to share a common PLL.
Please download the appropriate Quartus® II software version 10.1SP1 patch 1.77 from the following links:
You must either have previously installed the Quartus II 10.1 SP1 software or must install the Quartus II 10.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.
After you install the patch, please regenerate your Triple Speed Ethernet MegaCore® before you compile your design.