Article ID: 000086031 Content Type: Troubleshooting Last Reviewed: 08/29/2012

Why multiple Triple Speed Ethernet IP MegaCore instances with LVDS I/O fail to share the same PLL?

Environment

  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    It is due to the reason that each LVDS’s PLL reset input is driven by separate Triple Speed Ethernet ’s LVDS reset sequence logic and causes the reset input for each LVDS’s PLL undriven by the same reset input source.

    The following patch provides a solution to ensure different LVDS channels from different Triple Speed Ethernet IP MegaCore functions able to share a common PLL.

    Please download the appropriate Quartus® II software version 10.1SP1 patch 1.77 from the following links:

    Quartus II software version 10.1SP1 patch 1.77 for Windows

    Quartus II software version 10.1SP1 patch 1.77 for Linux

    Quartus II software version 10.1SP1 ReadMe for patch 1.77

    Caution:

    You must either have previously installed the Quartus II 10.1 SP1 software or must  install the Quartus II 10.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.

    After you install the patch, please regenerate your Triple Speed Ethernet MegaCore® before you compile your design.

     

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices