Article ID: 000081487 Content Type: Troubleshooting Last Reviewed: 06/04/2013

Can the DDR3 mem_reset_n signal be controlled by a user-accessible register?

Environment

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Description No, there is no user-accessible register to control the state of the mem_reset_n signal. The user can assert mem_reset_n by asserting the global_reset_n or soft_reset_n inputs to the controller. The length of time the mem_reset_n is asserted active-low is under the control of the DDR3 controller.
Resolution

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