Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does Timequest Report DDR not display the timing margin results of slave interfaces for UniPHY memory interface IP?

Description

You may also see these type of warning messages :

Warning (332087): The master clock for this clock assignment could not be derived.  Clock: <mem_ck_name> was not created.

Warning (332049): Ignored set_output_delay at <IP_name>_p0.sdc(407): Argument -clock with value [get_clocks {mem_dqs[1}] contains zero elements.

Workaround/Fix

For details of the flow, see the DLL and PLL Sharing Interface section in the Functional Description - UniPHY chapter in volume 3 of the External Memory Interface Handbook.

http://www.altera.com/literature/lit-external-memory-interface.jsp

In addition to the flow steps, if the master inst name contains a "\" in the hierarchy path name, it must be converted to "\\" to be recognized correctly in the <IP_name>_p0_timing.tcl script.

This issue is planned to be fixed in a future version of Quartus® II software.