Device Family: Arria® II GX, Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® III, Cyclone® III LS, Cyclone® IV E, Cyclone® IV GX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


Package effects when probing at the FPGA pin


When comparing signals probed at the memory device and the FPGA pins, it is observed on the oscilloscope that the signals at the FPGA pins have severe reflections when compared with the signals at the memory pins.  This is due to the package effect as explained below:  



1. The FPGA package has very long traces (e.g. ~50-150ps in Stratix® V). 

2. There is high capacitance at the buffer due to different IO standards supported by the FPGA.


Discrete Memory Component:

1. The package trace is relatively short (~10-30ps).

2. There is much lower capacitance (typically 1.8pF) at the buffer.


In FPGAs, the signal is terminated at the IO buffer and not at the pin.  Due to the large package trace length, probing at the FPGA pin is like probing in the middle of a transmission line with unusual termination. That is why reflections are seen on the scope.  Since the memory package trace is substantially shorter than that of the FPGA, the signal at the memory pin looks much better with less reflection. 


If the same signal is simulated using a board simulation tool (such as Hyperlynx), it can be seen that these effects disappear when observing the signal at the IO buffer.  For this reason, Altera recommends customers to perform board-level simulations for ISI and crosstalk instead of measuring it directly.


For more information on board simulation and calculating channel signal integrity please refer to the following page on Altera Wiki: Measuring Channel Signal Integrity (HTML)