Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is the DDR3 HMC with multiple MPFE ports hanging in simulation with ModelSim


DDR3 Hard Memory Controller (HMC) designs with 2 or more MPFE ports enabled may experience a lock-up condition on the Avalon bus when simulating with ModelSim® 10.1b or earlier. The avl_ready signal for each MPFE port will de-assert low and stay low forever causing the simulation to hang.


The workaround for this issue is to use ModelSim AE 10.1d or ModelSim SE 10.1d.