Device Family: Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Error (129001): Input port DQSDISABLEN on atom "|hierarchy|dqs_delay_chain", which is a stratixv_dqs_delay_chain primitive, is not legally connected and/or configured

Description

When you design with the ALTDQ_DQS2 block in a Stratix® V device, you may experience the following error when you synthesize the design:

Error (129001): Input port DQSDISABLEN on atom "|hierarchy|dqs_delay_chain", which is a stratixv_dqs_delay_chain primitive, is not legally connected and/or configured

There is a known issue which requires that the DQSDISABLEN and DQSENABLEN ports be connected to the same internal signal. Otherwise, you will get the synthesis error. 

Workaround/Fix

In the altdq_dqs2_stratixv.sv file, connect dqsdisablen and dqsenablen together to internal signal dqs_enable_int by changing the 2 lines as follows:

Change lines 967 & 968:

.dqsenable (dqs_enable_int),

.dqsdisablen (dqs_disable_int),

To

.dqsenable (dqs_enable_int),

.dqsdisablen (dqs_enable_int), 

 

Similarly, change lines 1117 & 1118:

.dqsenable (dqsn_enable_int),

.dqsdisablen (dqsn_disable_int),

To

.dqsenable (dqsn_enable_int),

.dqsdisablen (dqsn_enable_int),