Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Can I instantiate a master/slave DDR3 UniPHY example design in a top-level wrapper file?


Yes, you can instantiate a master/slave DDR3 UniPHY example design in your top-level wrapper file but you must change the master_instname in the <corename>_<slaveinstance>_p0_timing.tcl file to reflect the new hierarchy of the master. If this is not done, it will lead to several ignored constraint warnings during compilation and the DDR3 interfaces may not meet timing.

In Quartus® II software version 11.1 and later, when you generate an example design for a master DDR3 controller, the example design will contain two DDR3 instances. Instance IF0 is the master controller and instance IF1 is the slave controller. The slave controller's p0_timing.tcl file will have the master_instname variable set to the master's instance name like the following:

set ::master_instname "if0"

If you put the master/slave example design in a top-level wrapper file, you must modify the <corename>_<slaveinstance>_p0_timing.tcl file to reflect the new level of hierarchy. For example, if the DDR3 core is named "ddr3_test" and the example design is placed in a top-level wrapper with an instance name "ddr3_test_inst", then the master_instname variable in the ddr3_test_if1_p0_timing.tcl file must be modified like the following:

set ::master_instname "ddr3_test_inst|if0"

After making the change, recompile the design. You should no longer see ignored constraints for the DDR3 core, and the Report DDR report in TimeQuest should meet all timing.