Device Family: Arria® V, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I fix the core setup timing violations when I bond two DDR3 hard memory controllers from the top edge to bottom edge of the FPGA device?


When you bond two DDR3 hard memory controllers (HMC) located on the top and bottom edges and use pll_afi_half_clk as the clock for the MPFE port, you may get core setup timing violations between the bonding_in_* and bonding_out_* paths.


Although the MPFE clock is allowed to run up to half of the hard memory controller frequency, the maximum MPFE clock frequency depends on the core fabric performance. The path from bonding_out_* to bonding_in_* is routed through the core fabric and is too long, resulting in the timing violation.


Lower the MPFE clock frequency to achieve timing closure and increase the data width of the MPFE port to maintain the same bandwidth on the memory interface.