Device Family: Stratix® III

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR2 SDRAM Controller MegaCore supporting UniPHY

Why are the mem_dm pins unconstrained in my Stratix III DDR2 UniPHY design in 11.1?


Stratix®  III DDR2 UniPHY uses macro timing models for the DQ and DM pins so no output delay constraints are needed for those pins. Since these pins are unconstrained, the paths to these outputs should be cut in the SDC file. The Megawizard automatically adds the cut path assignments in the SDC for the DQ pins but does not add them for the DM pins leading to the unconstrained path message. 


If you don\'t want the DM pins to show up as unconstrained, you can add the cut path to the SDC file just like the DQ pins. Whether you do this or not has no impact on the actual implementation of the design.