Yes, there is an issue with power down request in DDR2 SDRAM in Quartus® II software version 9.0SP2 and older. The issue exists only when power down is requested (by asserting local_powerdn_req) before a write or read operation is requested. Hence, this issue does not affect Altera's DDR2 SDRAM High-Performance Example Design generated by the controller IP.
The issue manifests itself in functional simulation as the system hangs indefinitely when power down is requested. Power down will never be acknowledged meaning local_powerdn_ack will never go "high".
The workaround is to issue a dummy read or write before the request of power down.This issue is fixed in Quartus II software version 9.1 and later.