Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers

Area: Component, EMIF

Why is the Reserved Value in the Altera PHYLite Dynamic Reconfiguration Address Map different during simulation than the one published in the user guide?


If you refer to Altera PHYLite for Parallel Interfaces IP Core User Guide version 2015.01.28 and earlier, you may see the reserved value of Avalon Address R/W[23:21] stated in Table 11: Address Map is 3'h2. However , the simulation result shows 3'h4 which does not match with the user guide. The problem is due to the wrong value being stated in the user guide.


                                                          User Guide                             Simulation

Avalon Address [23:21]                3'h2  (incorrect)                     3'h4 (correct)





The Avalon Address R/W [23:21] in the user guide will be updated from 3\'h2 to 3\'h4 for all the features in the Address Map table.

This issue is scheduled to be fixed in the next release version of Altera PHYLite for Parallel Interfaces IP Core User Guide.

Table 11: Address Map

Feature                                                                   Avalon Address R/W

Pin Output Phase                                                 {id[3:0],3\'h4,lane_addr[7:0],pin{4:0],8\'D0}

Pin PVT Compensated Input Delay                   {id[3:0],3\'h4,lane_addr[7:0],4\'hC,lgc_sel[1:0],pin_off[2:0],4\'h0}

Strobe PVT compensated input delay              {id[3:0],3\'h4,lane_addr[7:0],4\'hC,lgc_sel[1:0],3\'h6,4\'h0}

Strobe enable phase                                           {id[3:0],3\'h4,lane_addr[7:0],4\'hC,lgc_sel[1:0],3\'h7,4\'h0}

Strobe enable delay                                            {id[3:0],3\'h4,lane_addr[7:0],4\'hC,9\'h008}

Read valid delay                                                   {id[3:0],3\'h4,lane_addr[7:0],4\'hC,9\'h00C}

Internal VREF Code                                               {id[3:0],3\'h4,lane_addr[7:0],4\'hC,9\'h014}