Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 Hilo Daughter Card

Why are some DDR4 signals unconstrained in TimeQuest?

Description

When designing an Arria® 10 DDR4 memory controller interface, you may see unconstrained DDR4 input and output ports. There should be false-path exceptions in the DDR4 SDC file for these signals.

 

 

Workaround/Fix

The workaround for this issue is to add the following assignments to the DDR4 SDC file under the FALSE PATH CONSTRAINTS section:

    set_false_path -to [get_ports {*dbi_n*}]
    set_false_path -from [get_ports {*dbi_n*}]
    set_false_path -from [get_ports {*alert_n*}]
    set_false_path -to [get_ports {*mem_ck*}]
    set_false_path -to [get_ports {*mem_ck_n*}]
    set_false_path -to [get_ports {*mem_dqs_n*}]

This issue will be fixed in a future version of the Quartus® II software.