Device Family: Intel® Arria® 10, Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR4 Hilo Daughter Card

Why does the time interval for four active windows during RTL simulation not match the tFAW setting in the Arria 10 FPGA DDR4 IP GUI?


Due to a rounding issue with the Arria® 10 FPGA DDR4 IP in the Quartus® II software version 14.1, the DDR4 four active windows time seen during RTL simulation might not match the tFAW setting in the DDR4 IP GUI, which will result in lower efficiency.

An example of when you may see this is with the IP Memory Clock Frequency parameter set to 1066.667MHz.


As a workaround, modify the memory clock frequency. In the example above, change the Memory Clock Frequency from 1066.667MHz to 1066.666MHz and then re-generate the DDR4 IP.

This issue is scheduled to be fixed in a future version of the Quartus II software.