Device Family: Intel® Arria® 10

Type: Answers

Area: Intellectual Property


Last Modified: February 24, 2017
Version Found: v15.1 Update 2
Version Fixed: v15.1 Update 2
IP Product: PCI Express Gen 3,2 or 1 x8,4,2,1 Hardened IP
Bug ID: 1506813470

How do I enable SKP Ordered Set Detection logic in the Intel® Arria® 10 Hard IP core for PCI* Express?

Description

Beginning in the Intel® Quartus® Prime v15.1.2 software, you can enable SKP Ordered Set detection logic in the Intel® Arria® 10 Hard IP for PCI* Express.


 

Workaround/Fix

To enable the SKP Ordered Set detection logic:
   1) Open the IP GUI
   2) Right click on the Intel® Arria® 10 Hard IP for PCI* Express banner and select Show Hidden Parameters
   3) Scroll down until you see the enable_skp_det parameter and enter "1"
   4) Do not modify any other hidden parameters
   5) Select Generate HDL

The SKP detection logic file skp_det_g3.v will be included in your Intel® Quartus® Prime file list for compilation.

You can monitor the skp_os signal from the IP core top-level interface. skp_os will assert any time scrambled data exactly matches a SKP pattern when in Gen3 speed.

Erroneous Skip Ordered Sets will cause the IP Core to enter the recovery state. Other possible causes for entering recovery are, a high bit error rate (BER) or excessive reference clock parts per million(ppm) difference.

For additional details on the SKP Ordered Set issue, see "Why does the Intel® Hard IP for PCI Express* in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again?".