Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property

IP Product: 10Gbps Ethernet MAC with 1588 MegaCore

Why does the rx_latency_adj_10g and tx_latency_adj_10g signal descriptions refer to 1g for the Arria V and Stratix V devices in the Altera Transceiver PHY IP User Guide?


Due to a mistake in "Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs" of the Altera® Transceiver PHY IP Core User Guide (PDF) the rx_latency_adj_10g and tx_latency_adj_10g signals refer to 1g for the Arria® V and Stratix® V devices.

The rx_latency_adj_10g and tx_latency_adj_10g signal signals should only refer to 10g.


This problem will be fixed in a future version of the Transceiver PHY User Guide (PDF).