Device Family: Arria® V GT, Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Rule C101: Gated clock should be implemented according to the Altera standard scheme

Description

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design. 

Rule C101: Gated clock should be implemented according to the Altera standard scheme ; <hierarchy>:altdq_dqs2_inst|dqsbusout

This warning is expected and can be safely ignored.

Workaround/Fix