Device Family: Arria® V GT, Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power

Description

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design.

Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; <hierarchy>:altdq_dqs2_inst|dqsbusout

This warning is expected and can be safely ignored.

Workaround/Fix