Device Family: Arria® V GT, Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Rule C105: Clock signal should be a global signal

Description

You may see the following warnings when running the Design Assistant tool in Quartus II software on your compiled HPS design.

Rule C105: Clock signal should be a global signal ;            <hierarchy>|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk 

Rule C105: Clock signal should be a global signal ; <hierarchy>|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk

These warnings are expected and can be safely ignored.

Workaround/Fix