Device Family: Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Cyclone V SoC FPGA Development Kit

Why do I get fitter errors when compiling a Qsys DDR3 UniPHY based controller design?

Description

You may see the following errors when trying to compile HPS design  generated in Qsys design

Error: Input port DATAIN on atom "<Hierarchy>.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured
    Info (129003): Input port DATAIN is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
Error: Input port ENA on atom "<Hierarchy>.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured
    Info (129003): Input port ENA is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
Error: Input port UPDATE on atom "<Hierarchy>.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured
    Info (129003): Input port UPDATE is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal

 

Workaround/Fix

This is caused by trying to use the Qsys system directly using deferred generation. i.e your .qsf file includes the .qsys file and the IP is generated on the fly. This doesn’t work in a current version of Quartus II software.

The correct design flow is to replace the .qsys file in your project file list with the .qip file then recompile your design.