Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why are bidirectional mem_dbi_n ports created when the 'Enable DM Pins' option is selected in the Arria 10 DDR4 controller?

Description

You may see bidirectional mem_dbi_n ports exposed when you create an Arria® 10 DDR4 controller with the 'Enable DM pins' options selected inside the IP Catalog GUI.

In DDR4, the data mask (DM) and data bus inversion (DBI) features share the same pins, but cannot be enabled at the same time. When the DM or DBI feature is selected, the bidirectional mem_dbi_n ports will be exposed.

Workaround/Fix