Type: Answers


IP Product: PCI Express Gen 3,2 or 1 x8,4,2,1 Hardened IP

*** Fatal Error: Segment Violation at (nil)

Description

When you enable the SKP Detection logic in Gen3 mode for the Arria® 10 Hard IP for PCI® Express in Quartus® Prime 15.1.2 this fatal error may be seen.

The timing constraint file, altera_pcie_a10_skp.sdc, is auto generated for the SKP Detection logic. If this .sdc file is read before the PLL clocks are derived, you will encounter this Quartus Internal Error.

Workaround/Fix

To work around the Quartus Internal Error, read the altera_pcie_a10_skp.sdc file after the corresponding PLL clocks are derived. You should run derive_pll_clocks first before running this .sdc file. Ensure the .sdc file that includes derive_pll_clocks is listed before this file.

This problem is scheduled to be fixed in a future release of the Quartus Prime software.