You may see the above synthesis error when compiling an Arria® V DDR3 soft controller design created with Qsys in the Quartus® II software version 13.0 or later. The error occurs when logic inside the DDR3 controller is optimized away because the Avalon signals were not properly connected to an Avalon Master and an Avalon Master clock source.
Device Family: Arria® V, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX
Area: EMIF, Intellectual Property
IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY
Make sure the Avalon interface is properly connected to an Avalon Master and an Avalon Master clock source.