Device Family: Stratix® III

Type: Answers

Area: Component, EMIF


IP Product: DDR2 SDRAM Controller supporting ALTMEMPHY

Can Half-Rate DDR or DDR2 Altmemphy Datapaths be interleaved in Stratix III and Stratix IV devices?

Description

No, in Stratix® III and Stratix IV devices the half-rate resynchronization clock is cascaded from one DQ group to the next directly in the IOE. Hence Half-Rate Datapaths using the Altera Altmemphy Must Not be Interleaved with each other.

This Requirement does not effect Full-Rate Altmemphy Datapaths. Refer to AN 435: Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices (PDF) for more information.