Device Family: Stratix® V, Stratix® V GX

Type: Answers

Area: Component, HSIO

What is the read latency of an M20K ROM that must be accounted for when performing MIF-based streaming dynamic reconfiguration Stratix V GX devices?


When implementing MIF-based dynamic reconfiguration on Stratix® V GX devices, and reading data from an M20K based ROM, the read latency is one clock cycle if the ROM output is unregistered, or two clock cycles if the output is registered.