Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GZ, Intel® Stratix® 10 GX, Intel® Stratix® 10 SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: Low Latency 10Gbps Ethernet MAC 1588 opt

How should I read 36-bit counter registers of Low Latency 10GbE and Low Latency 40 - 100GbE MAC IP core to obtain correct counter value?

Description

To read 36-bit registers in the Low Latency 10, 40 and 100GbE MAC IP cores, read the lower 32-bit first, followed by upper 4-bit.

For self-clear (RC) counter registers such as register-based counters, the lower 32-bit must be read first, followed by the upper 4-bit to obtain correct values.

For non-self-clear (RO) counter registers such as memory-based counters, when the lower 32-bit are read, the upper 4-bit are captured. Therefore, the misalignment of the lower 32-bit and the upper 4-bit values due to carry to the upper 4-bit during counter read will not happen.