Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Arria® II GX

Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Intel® Cyclone®

Device Family: Cyclone® II

Device Family: Cyclone® III

Device Family: Cyclone® III LS

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Device Family: Cyclone® IV GX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

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Device Family: Cyclone® V SE

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Device Family: Stratix® II

Device Family: Stratix® II GX

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Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Component



Which clock edge is used to launch or capture Active Serial (AS) signals in the Serial Flash Loader (SFL) IP ?

Description

When programming a Serial Configuration (EPCS) device, a Quad-Serial Configuration (EPCQ) device or an EPCQ-L Serial Configuration device using the Serial Flash Loader (SFL) IP, Active Serial (AS) signals from/to the FPGA are launched or captured at the following clock edge: 

  • nCS and ASDO (DATA0) from the FPGA are launched on the falling edge of DCLK.
  • DATA (DATA1) to the FPGA is captured on the rising edge of DCLK.

For the overall timing relationship for AS configuration, refer to the respective device handbook or device datasheet.